library IEEE;
use ieee.std_logic_1164.all;
use work.package_micro_simple.all;

entity micro_simple is
	generic(GND			: std_logic_vector (7 downto 0) := "00000000"
		   );
	port(data_in       : in	std_logic_vector (7 downto 0);
		 rst, clk      : in   std_logic;
		 data_out,addr : out	std_logic_vector (7 downto 0);
		 rd, wr		   : out std_logic
		 );
end micro_simple;

architecture micro_arch of micro_simple is
	signal ir_out : std_logic_vector(7 downto 0);
	signal tc_out : std_logic_vector(7 downto 0);
	signal dr_out : std_logic_vector(7 downto 0);
	signal ac_out : std_logic_vector(7 downto 0);
	signal ar_out : std_logic_vector(7 downto 0);
	signal pc_out : std_logic_vector(7 downto 0);
	signal mux2_out : std_logic_vector(7 downto 0);
	signal alu1_out : std_logic_vector(7 downto 0);
	signal microbus : std_logic_vector(15 downto 0);

begin
	tc:reg_8 port map (GND, clk, rst, microbus(1), microbus(0), tc_out);
	ir:reg_8 port map (dr_out, clk, rst, '0', microbus(2), ir_out);
	ar:reg_8 port map (dr_out, clk, rst, '0', microbus(3), ar_out);
	pc:reg_8 port map (dr_out, clk, rst, microbus(5), microbus(4), pc_out);
	dr:reg_8 port map (mux2_out, clk, rst, '0', microbus(13), dr_out);
	ac:reg_8 port map (alu1_out, clk, rst, '0', microbus(11), ac_out);

	mux1:mux port map (pc_out,ar_out,microbus(6),addr);
	mux2:mux port map (data_in, alu1_out, microbus(12), mux2_out);
	
	alu1:alu port map (ac_out, dr_out, microbus(10 downto 7), '0', alu1_out);
	
	micro:micro_codigo port map (ir_out, tc_out, microbus);
	
	rd <= microbus(14);
	wr <= microbus(15);
	
end micro_arch;